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| ! ! ? as7c164 (5v version) commercial temperature organization: 8,192 words 8 bits center power and ground pins high speed - 12/15/20 ns address access time - 6/7/8 ns output enable access time low power consumption: active - 550 mw (as7c164) / max @ 12 ns low power consumption: standby - 11 mw (as7c164) / max cmos i/o 2.0v data retention easy memory expansion with ce1 , ce2, oe inputs ttl-compatible, three-state i/o 28-pin jedec standard package - 300 mil pdip and soj esd protection 2000 volts latch-up current 200 ma " # $ a 5 a 0 128648 array (65,536) input buffer a1 a2 a3 a4 a10 a11 a12 a 6 a 7 a 8 a 9 i/o0 i/o7 v cc gnd oe ce1 we column decoder row decoder control circuit sense amp ce2 % 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 vcc we ce2 a8 a9 a11 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 nc a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd 28-pin pdip, soj (300 ml) 16 15 as7c164 -12 -15 -20 unit maximum address access time 12 15 20 ns maximum output enable access time 6 7 8 ns maximum operating current 110 100 90 ma maximum cmos standby current 2.0 2.0 2.0 ma ! ! the as7c164 is a high performance cmos 65,536-bit static random access memory (sram) device organized as 8,192 words 8 bits. it is designed for memory applications where fast data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 12/15/20 ns with output enable access times (t oe ) of 6/7/8 ns are ideal for high performance applications. active high and low chip enables (ce1 , ce2) permit easy memory expansion with multiple-bank memory systems. when ce1 is high or ce2 is low the device enters standby mode. the standard as7c164 is guaranteed not to exceed 11.0 mw power consumption in standby mode, and typically requires only 250 w; it offers 2.0v data retention with maximum power of 120 w. a write cycle is accomplished by asserting write enable (we ) and both chip enables (ce1 , ce2). data on the input pins i/o0-i/o7 is written on the rising edge of we (write cycle 1) or the active-to-inactive edge of ce1 or ce2 (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and both chip enables (ce1 , ce2), with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input address. when either chip enable or output enable is inactive, or write ena ble is active, output drivers stay in high-impedance mode. all chip inputs and outputs are ttl-compatible, and operation is from a single 5v supply. the as7c164 is packaged in all high v olume industry standard packages. # & note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional oper- ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ' # key: x = don?t care, l = low, h = high parameter device symbol min max unit vol t ag e o n v cc relative to gnd as7c164 v t1 ?0.50 +7.0 v voltage on any pin relative to gnd v t2 ?0.50 v cc + 0.50 v power dissipation p d ?1.0w storage temperature (plastic) t stg ?65 +150 o c ambient temperature with v cc applied t bias ?55 +125 o c dc current into outputs (low) i out ?20ma ce1 ce2 we oe data mode hxxxhigh zstandby (i sb , i sb1 ) xlxxhigh zstandby (i sb , i sb1 ) lhhhhigh zoutput disable (i cc ) lhhld out read (i cc ) lhlxd in write (i cc ) ! ( ) * + , + - ./01 ' -2 1 3 - 45.64 ", parameter device symbol min typical max unit supply voltage as7c164 v cc 4.5 5.0 5.5 v input voltage as7c164 v ih 2.2 ? v cc +1 v v il ?0.5 * * v il min = ?3.0v for pulse width less than t rc /2. ?0.8v ambient operating temperature as7c164 t a 0?70 o c parameter symbol test conditions device -12 -15 -20 unit min max min max min max input leakage current | i li | v cc = max, v in = gnd to v cc ?1?1?1a output leakage current | i lo | v cc = max, ce1 = v ih or ce2 = v il , v out = gnd to v cc ?1?1?1a operating power supply current i cc v cc = max, ce1 = v il , ce2 = v ih , f = f max, i out = 0 ma as7c164 ? 110 ? 100 ? 90 ma standby power supply current i sb v cc = max, ce1 = v ih or ce2 = v il , f = f max as7c164 ? 30 ? 25 ? 25 ma i sb1 v cc = max, ce1 v cc ?0.2v or ce2 0.2v, v in 0.2v or v in v cc ?0.2v, f = 0 as7c164?2.0?2.0?2.0ma output voltage v ol i ol = 8 ma, v cc = min ? 0.4 ? 0.4 ? 0.4 v v oh i oh = ?4 ma, v cc = min 2.4 ? 2.4 ? 2.4 ? v parameter symbol signals test conditions max unit input capacitance c in a, ce1 , ce2, we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf ! 7 ) + , 8 9 9 ) 9 + , ) 9 +: : , parameter symbol -12 -15 -20 unit notes min max min max min max read cycle time t rc 12 ? 15 ? 20 ? ns address access time t aa ?12?15?20 ns3 chip enable (ce1 ) access time t ace1 ?12?15?20 ns3, 12 chip enable (ce2) access time t ace2 ?12?15?20 ns3, 12 output enable (oe ) access time t oe ?6?7?8 ns output hold from address change t oh 3?3?3? ns5 ce1 low to output in low z t clz1 3?3?3? ns4, 5, 12 ce2 high to output in low z t clz2 3?3?3? ns4, 5, 12 ce1 high to output in high z t chz1 ?3?4?5 ns4, 5, 12 ce2 low to output in high z t chz2 ?3?4?5 ns4, 5, 12 oe low to output in low z t olz 0?0?0? ns4, 5 oe high to output in high z t ohz ?3?4?5 ns4, 5 power up time t pu 0?0?0? ns4, 5, 12 power down time t pd ? 12 ? 15 ? 20 ns 4, 5, 12 undefined/don?t care falling input rising input address d out data valid t oh t aa t rc current supply ce2 oe d out t oe t olz t ace1, t ace2 t chz1, t chz2 t clz1, t clz2 t pu t pd i cc i sb 50% 50% t ohz data valid t rc 1 ce1 ! 2 ; + , ; 9 +;: , ; 9 +: : , parameter symbol -12 -15 -20 unit notes minmaxminmaxminmax write cycle time t wc 12 ? 15 ? 20 ? ns chip enable (ce1 ) to write end t cw1 9 ? 10 ? 12 ? ns 12 chip enable (ce2) to write end t cw2 9 ? 10 ? 12 ? ns 12 address setup to write end t aw 9?10?12? ns address setup time t as 0?0?0? ns12 write pulse width t wp 8?9?12? ns write recovery time t wr 0?0?0? ns address hold from write end t ah 0?0?0? ns data valid to write end t dw 6?7?8? ns data hold time t dh 0?0?0? ns4, 5 write enable to output in high z t wz ?5?5?5 ns4, 5 output active from write end t ow 3?3?3? ns4, 5 t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t wr t aw address ce1 we d out t cw1, t cw2 t wp t dw t dh t ah t wz t wc t as ce2 data valid d in t wr ! < * + , * 9 4 1during v cc power-up, a pull-up resistor to v cc on ce1 is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions , figures a, b, and c. 4t clz and t chz are specified with cl = 5pf as in figures b or c. transition is measured 500mv from steady-state voltage. 5 this parameter is guaranteed, but not 100% tested. 6we is high for read cycle. 7ce1 and oe are low and ce2 is high for read cycle. 8 address valid prior to or coincident with ce1 transition low and ce2 transition high. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 ce1 or we must be high or ce2 low during address transitions. either ce or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 ce1 and ce2 have identical timing. 13 2v data retention applies to the commercial operating range only. 14 c = 30pf, except on high z and low z parameters, where c = 5pf. parameter symbol test conditions min max unit v cc for data retention v dr v cc = 2.0v ce1 v cc ?0.2v or ce2 0.2v 2.0 ? v data retention current i ccdr ?60a chip enable to data retention time t cdr 0?ns operation recovery time t r t rc ?ns v cc ce1 t r t cdr data retention mode v cc v cc v dr 2.0v v ih v ih v dr cs2 t r t cdr v ih v ih v dr - output load: see figure b or figure c. - input pulse level: gnd to 3.0v. see figure a. - input rise and fall times: 2 ns. see figure a. - input and output timing reference levels: 1.5v. 10% 90% 10% 90% gnd +3.0v figure a: input pulse 2ns 255 ? c (14) 480 ? d gnd +5v figure b: 5v output lo 255 ? c (14) 320 ? d gnd +5v figure c: 3.3v output load 168 ? thevenin equivalent: d +1.728v (5v) ! = ' * supply voltage (v) min max nominal 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb ambient temperature (c) ?55 80 125 35 ?10 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb vs. ambient temperature t a vs. supply voltage v cc i cc i sb i cc i sb ambient temperature (c) -55 80 125 35 -10 0.2 1 0.04 5 25 625 normalized i sb1 (log scale) normalized supply current i sb1 vs. ambient temperature t a v cc = v cc (nominal) supply voltage (v) min max nominal 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa ambient temperature (c) ?55 80 125 35 ?10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa cycle frequency (mhz) 075 100 50 25 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current i cc vs. ambient temperature t a vs. cycle frequency 1/t rc , 1/t wc vs. supply voltage v cc v cc = v cc (nominal) t a = 25c v cc = v cc (nominal) t a = 25c output voltage (v) v cc 0 20 60 80 40 100 120 140 output source current (ma) output source current i oh output voltage (v) v cc output sink current (ma) output sink current i ol vs. output voltage v ol vs. output voltage v oh 0 20 60 80 40 100 120 140 v cc = v cc (nominal)pl t a = 25c v cc = v cc (nominal) t a = 25c capacitance (pf) 0 750 1000 500 250 0 5 15 20 10 25 30 35 change in t aa (ns) typical access time change ? t aa vs. output capacitive loading v cc = v cc (nominal) 00 ! ? copyright alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time withou t notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to chang e or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpo se, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusivel y according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use %$ 5 % # package\ access time volt/temp 12 ns 15 ns 20 ns plastic dip\300 ml 5v commercial as7c164-12pc as7c164-15pc AS7C164-20PC plastic soj\300 ml 5v commercial as7c164-12jc as7c164-15jc as7c164-20jc as7c 164 x ?xx x c sram prefix device number blank = standard power access time package code: p=pdip 300 mil j=soj 300 mil commercial temperature range, 0c to 70c c ea seating b a1 e1 e d e l s plane b a pin 1 28-pin pdip min max a - 0.175 a1 0.010 - b 0.058 0.064 b 0.016 0.022 c 0.008 0.014 d - 1.400 e 0.295 0.320 e1 0.278 0.298 e 0.100 bsc ea 0.330 0.370 l 0.120 0.140 0 15 s - 0.055 28-pin soj in mil min max a - 0.140 a1 0.025 - a2 0.095 0.105 b 0.028 typ b 0.018 typ c 0.010 typ d - 0.730 e 0.245 0.285 e1 0.295 0.305 e2 0.327 0.347 e 0.050 bsc seating plane 300 mil 28-pin pdip 300 mil 28-pin soj |
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